Verification of UML Statechart Models of Embedded Systems

The test and verification are essential phases of any system development. With the enlargement of the size and complexity of the system under development the importance of these tasks increases. Traditionally the system development is divided into DQDO\VLVV GHVLJQ and LPSOHPHQWDWLRQ phases regardless of the development process applied (Fig. 1). The system development process is typically accompanied by the occurrence of design and implementation faults. To avoid these faults the implementation phase is followed by a WHVW phase. The test phase is intended to recover the differences between the GHVLJQ and the LPSOHPHQWHGGV\VWHP, i.e. to find the faults that arise in the implementation phase. The activities of the test phase include WHVWWFDVHHGHILQLWLRQ and WHVWWFDVHHH[HFXWLRQ. The test phase can substantially be accelerated by the automation of these activities. The automation of test case execution on the basis of the design is often supported by CASE tools [1]. The automated definition of the test cases could be implemented only in the case when the design itself is described by a formal model [3,4]. These automated tools are essential in the development of large systems since they can efficiently accelerate the execution of the time-consuming testing. The faults of implementation can be discovered by the test phase, however, the faults of the design may remain undiscovered. In order to recognize these faults, the development process has to be completed by the GHVLJQQ YHULILFDWLRQ phase. The goal of design verification is to find the faults in the design itself. The fault may be instantiated as an LQFRQVLVWHQWWGHVLJQ or as an